The ATmega48A/PA/88A/PA/168A/PA/328/P features a 10-bit successive approximation ADC. The ADC is connected to an 8-channel Analog Multiplexer which allows eight single-ended voltage inputs constructed from the pins of Port A. The single-ended voltage inputs refer to 0V (GND).
The ADC uses registers ADMUX, ADCSRA, ADCL, ADCH, ADCSRB and DIDR0 to configure the hardware and to do analog to digital conversion. Anlong with register configuration, ADC hardware also needs separate analog supply voltage pin, AVCC. AVCC must not differ more than ±0.3V from VCC. Internal reference voltages can be set at 1.1V or AVCC. When the voltage reference is selected externally the AREF pin is connected with a capacitor for better noise performance.
ADMUX – ADC Multiplexer Selection Register
• Bit 7:6 – REFS[1:0]: Reference Selection Bits
These bits select the voltage reference for the ADC. The internal voltage reference options may not be used if an external reference voltage is being applied to the AREF pin.
|REFS1||REFS0||Voltage Reference Selection|
|0||0||AREF, Internal VREF turned off|
|0||1||AVCC with external capacitor at AREF pin|
|1||1||Internal 1.1V Voltage Reference with external capacitor at AREF pin|
• Bit 5 – ADLAR: ADC Left Adjust Result
The ADLAR bit affects the presentation of the ADC conversion result in the ADC Data Register. Write one to ADLAR to left adjust the result. Otherwise, the result is right adjusted.
• Bits 3:0 – MUX[3:0]: Analog Channel Selection Bits
The value of these bits selects which analog inputs are connected to the ADC.
|MUX[3:0]||Single Ended Input|
ADCSRA – ADC Control and Status Register A
• Bit 7 – ADEN: ADC Enable
Writing this bit to one enables the ADC. By writing it to zero, the ADC is turned off. Turning the ADC off while a conversion is in progress, will terminate this conversion.
• Bit 6 – ADSC: ADC Start Conversion
In Single Conversion mode, write this bit to one to start each conversion. In Free Running mode, write this bit to one will take 25 ADC clock cycles instead of the normal 13 This first conversion performs initialization of the ADC. ADSC will read as one as long as a conversion is in progress. When the conversion is complete, it returns to zero.
• Bit 5 – ADATE: ADC Auto Trigger Enable
When this bit is written to one, Auto Triggering of the ADC is enabled. The ADC will start a conversion on a positive edge of the selected trigger signal. The trigger source is selected by setting the ADC Trigger Select bits, ADTS in
• Bit 4 – ADIF: ADC Interrupt Flag
This bit is set when an ADC conversion completes and the Data Registers are updated. The ADC Conversion Complete Interrupt is executed if the ADIE bit and the I-bit in SREG are set. ADIF is cleared by hardware when
executing the corresponding interrupt handling vector.
• Bit 3 – ADIE: ADC Interrupt Enable
When this bit is written to one and the I-bit in SREG is set, the ADC Conversion Complete Interrupt is activated.
• Bits 2:0 – ADPS[2:0]: ADC Prescaler Select Bits
These bits determine the division factor between the system clock frequency and the input clock to the ADC.
ADCL and ADCH – The ADC Data Register
ADLAR = 0
ADLAR = 1
When an ADC conversion is complete, the result is found in these two registers. Total of 10 bits of conversion result is stored in these two registers.
ADCSRB – ADC Control and Status Register B
• Bit 2:0 – ADTS[2:0]: ADC Auto Trigger Source
If ADATE in ADCSRA is written to one, the value of these bits selects which source will trigger an ADC conversion.
|0||0||0||Free Running mode|
|0||1||0||External Interrupt Request 0|
|0||1||1||Timer/Counter0 Compare Match A|
|1||0||1||Timer/Counter1 Compare Match B|
|1||1||1||Timer/Counter1 Capture Event|
DIDR0 – Digital Input Disable Register 0
• Bit 5:0 – ADC5D…ADC0D: ADC5…0 Digital Input Disable
When this bit is written logic one, the digital input buffer on the corresponding ADC pin is disabled. The corresponding PIN Register bit will always read as zero when this bit is set. When an analog signal is applied to the ADC5…0 pin and the digital input from this pin is not needed, this bit should be written logic one to reduce power consumption in the digital input buffer.