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Also visit the Release Page for Register Level Embedded C Hardware Abstraction Library and Code for AVR.
The I2C / 2-wire Serial Interface (TWI) hardware in the ATmega48A/PA/88A/PA/168A/PA/328/P microcontroller uses registers TWBR, TWCR, TWSR, TWDR, TWAR and TWAMR to configure the hardware and to transmit and receive data. Below are the register descriptions. Atmel uses the term TWI / Two Wire Interface for avoiding licensing conflicts. TWI is compatable with I2C protocol.
TWBR – TWI Bit Rate Register
• Bits 7…0 – TWI Bit Rate Register
TWBR selects the division factor for the bit rate generator. The bit rate generator is a frequency divider which generates the SCL clock frequency in the Master modes.
SCL frequency = CPU clock frequency / (16 + 2 * TWBR * PrescalerValue)
TWCR – TWI Control Register
The TWCR is used to control the operation of the I2C / TWI. It is used to enable the I2C / TWI, to initiate a master access by applying a START condition to the bus, to generate a receiver acknowledge, to generate a STOP condition, and to control bus collisions.
• Bit 7 – TWINT: TWI Interrupt Flag
This bit is set by hardware when the TWI has finished its current job and expects application software response. When the TWINT Flag is set, the SCL LOW period is stretched. The TWINT Flag must be cleared by software by writing a logic one to it. This flag is not automatically cleared by hardware when executing the interrupt routine. Clearing this flag resumes the operation of the TWI.
• Bit 6 – TWEA: TWI Enable Acknowledge Bit
The TWEA bit controls the generation of the acknowledge pulse. If the TWEA bit is written to one, the ACK pulse is generated on the TWI bus if the following conditions are met:
1. The device’s own slave address has been received
2. A general call has been received, while the TWGCE bit in the TWAR is set
3. A data byte has been received in master receiver or slave receiver mode
By writing the TWEA bit to zero, the device can be disconnected from the 2-wire serial bus temporarily.
• Bit 5 – TWSTA: TWI START Condition Bit
The application software need to write the TWSTA bit to one when it desires to become a master on the 2-wire Serial Bus. The TWI hardware generates a START condition on the bus if it is free. If the bus is not free, the TWI waits until a STOP condition is detected, and then generates a new START condition to claim the bus master status. TWSTA must be cleared by software when the START condition has been transmitted.
• Bit 4 – TWSTO: TWI STOP Condition Bit
When the TWSTO bit is set the TWi hardware will generate a STOP condition on the 2-wire bus. When the STOP condition is executed on the bus, the TWSTO bit is cleared automatically. In slave mode, setting the TWSTO bit is used to recover from an error condition. This releases the SCL and SDA lines to a high impedance state.
• Bit 3 – TWWC: TWI Write Collision Flag
The TWWC bit is set when attempting to write to the TWI Data Register – TWDR when TWINT is low. This flag is cleared by writing the TWDR Register when TWINT is high.
• Bit 2 – TWEN: TWI Enable Bit
The TWEN bit enables I2C / TWI operation and activates the TWI interface. If this bit is written to zero, the TWI is switched off and all TWI transmissions are terminated, regardless of any ongoing operation.
• Bit 1 – Reserved
This bit is a reserved bit and will always read as zero.
• Bit 0 – TWIE: TWI Interrupt Enable
When this bit is written to one, and the I-bit in SREG is set, the TWI interrupt is enabled.
TWSR – TWI Status Register
• Bits 7:3 – TWS: TWI Status
These 5 bits reflect the status of the TWI logic and the 2-wire serial bus.
• Bit 2 – Reserved
This bit is reserved and will always read as zero.
• Bits 1:0 – TWPS: TWI Prescaler Bits
These bits can be read and written, and control the bit rate prescaler
TWDR – TWI Data Register
In Transmit mode, TWDR contains the next byte to be transmitted. In Receive mode, the TWDR contains the last byte received. Data can be written when the TWI Interrupt Flag (TWINT) is set by hardware. The data in TWDR remains stable as long as TWINT is set. While data is shifted out on the bus. In the case of a lost bus arbitration, no data is lost in the transition from master to slave. Handling of the ACK bit is controlled automatically by the TWI logic, the CPU cannot access the ACK bit directly.
• Bits 7:0 – TWD: TWI Data Register
These eight bits constitute the next data byte to be transmitted, or the latest data byte received on the 2-wire Serial Bus.
TWAR – TWI (Slave) Address Register
The TWAR should be loaded with the 7-bit slave address (in the seven most significant bits of TWAR) to which the TWI will respond when programmed as a slave transmitter or receiver, and not needed in the master modes. In
multi master systems, TWAR must be set.
• Bits 7:1 – TWA: TWI (Slave) Address Register
These seven bits constitute the slave address of the TWI unit.
• Bit 0 – TWGCE: TWI General Call Recognition Enable Bit
If set, this bit enables the recognition of a General Call given over the 2-wire Serial Bus.
TWAMR – TWI (Slave) Address Mask Register
• Bits 7:1 – TWAM: TWI Address Mask
The TWAMR can be loaded with a 7-bit Salve Address mask. Each of the bits in TWAMR can mask (disable) the corresponding address bits in the TWI Address Register (TWAR). If the mask bit is set to one then the address
match logic ignores the compare between the incoming address bit and the corresponding bit in TWAR.
• Bit 0 – Reserved
This bit is an unused bit in the ATmega48A/PA/88A/PA/168A/PA/328/P, and will always read as zero.